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83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count product specification supersedes data of 1998 jan 19 ic20 data handbook 1998 may 01 integrated circuits
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 2 1998 may 01 853-0599 19326 description the philips 83c751/87C751 offers the advantages of the 80c51 architecture in a small package and at low cost. the 8xc751 microcontroller is fabricated with philips high-density cmos technology. philips epitaxial substrate minimizes cmos latch-up sensitivity. the 8xc751 contains a 2k 8 rom (83c751) eprom (87C751), a 64 8 ram, 19 i/o lines, a 16-bit auto-reload counter/timer, a five-source, fixed-priority level interrupt structure, a bidirectional inter-integrated circuit (i 2 c) serial bus interface, and an on-chip oscillator. the on-board inter-integrated circuit (i 2 c) bus interface allows the 8xc751 to operate as a master or slave device on the i 2 c small area network. this capability facilitates i/o and ram expansion, access to eeprom, processor-to-processor communication, and efficient interface to a wide variety of dedicated i 2 c peripherals. features ? 80c51 based architecture ? inter-integrated circuit (i 2 c) serial bus interface ? small package sizes 24-pin dip (300 mil askinny dipo) 24-pin shrink small outline package 28-pin plcc ? 87C751 available in one-time programmable plastic packages ? wide oscillator frequency range ? low power consumption: normal operation: less than 11ma @ 5v, 12mhz idle mode power-down mode ? 2k 8 rom (83c751) 2k 8 eprom (87C751) ? 64 8 ram ? 16-bit auto reloadable counter/timer ? fixed-rate timer ? boolean processor ? cmos and ttl compatible ? well suited for logic replacement, consumer and industrial applications ? led drive outputs pin configurations 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 p3.4/a4 p3.3/a3 p3.2/a2/a10 p3.1/a1/a9 p3.0/a0/a8 p0.2/v pp p0.1/sda/oepgm rst x2 x1 v ss p0.0/scl/asel p1.0/d0 p1.1/d1 p1.2/d2 p1.3/d3 p1.4/d4 p1.5/int0 /d5 p1.6/int1 /d6 p1.7/t0/d7 p3.7/a7 p3.6/a6 p3.5/a5 v cc plastic dual in-line package and shrink small outline package plastic leaded chip carrier 4126 5 11 25 19 12 18 pin function 1 p3.4/a4 2 p3.3/a3 3 p3.2/a2/a10 4 p3.1/a1/a9 5 nc* 6 p3.0/a0/a8 7 p0.2/v pp 8 p0.1/sda/oe-pgm 9 p0.0//sclasel su00315 * do not connect pinfunction 10 nc* 11 rst 12 x2 13 x1 14 v ss 15 p1.0/d0 16 p1.1/d1 17 p1.2/d2 18 p1.3/d3 pin function 19 p1.4/d4 20 p1.5/int0 /d5 21 nc* 22 nc* 23 p1.6/int1 /d6 24 p1.7/t0/d7 25 p3.7/a7 26 p3.6/a6 27 p3.5/a5 28 v cc
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 3 ordering information rom eprom 1 temperature range c and package frequency drawing number s83c7511n24 s87C7511n24 otp 0 to +70, plastic dual in-line package 3.5 to 12mhz sot222-1 s83c7512n24 s87C7512n24 otp 40 to +85, plastic dual in-line package 3.5 to 12mhz sot222-1 s83c7514n24 s87C7514n24 otp 0 to +70, plastic dual in-line package 3.5 to 16mhz sot222-1 s83c7515n24 s87C7515n24 otp 40 to +85, plastic dual in-line package 3.5 to 16mhz sot222-1 s83c7511a28 s87C7511a28 otp 0 to +70, plastic leaded chip carrier 3.5 to 12mhz sot261-3 s83c7512a28 s87C7512a28 otp 40 to +85, plastic leaded chip carrier 3.5 to 12mhz sot261-3 s83c7514a28 s87C7514a28 otp 0 to +70, plastic leaded chip carrier 3.5 to 16mhz sot261-3 s83c7515a28 s87C7515a28 otp 40 to +85, plastic leaded chip carrier 3.5 to 16mhz sot261-3 s83c7511db s87C7511db otp 0 to +70, shrink small outline package 3.5 to 12mhz sot340-1 s83c7514db s87C7514db otp 0 to +70, shrink small outline package 3.5 to 16mhz sot340-1 note: 1. otp = one time programmable eprom.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 4 block diagram rst x1 x2 v cc v ss ram rom/ eprom acc tmp2 tmp1 alu instruction register pd oscillator psw buffer dptr pcon i2cfg i2sta tcon i2dat i2con ie th0 tl0 rth rtl interrupt, serial port and timer blocks i 2 c control p1.0p1.7 p3.0p3.7 p0.0p0.2 port 0 drivers ram addr register port 0 latch stack pointer program address register pc incre- menter program counter port 3 drivers port 1 drivers port 3 latch port 1 latch timing and control b register su00316
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 5 pin descriptions pin no. mnemonic dip/ ssop lcc type name and function v ss 12 14 i circuit ground potential v cc 24 28 i supply voltage during normal, idle, and power-down operation. p0.0p0.2 86 97 i/o port 0: port 0 is a 3-bit open-drain, bidirectional port. port 0 pins that have 1s written to them float, and in that state can be used as high-impedance inputs. port 0 also serves as the serial i 2 c interface. when this feature is activated by software, scl and sda are driven low in accordance with the i 2 c protocol. these pins are driven low if the port register bit is written with a 0 or if the i 2 c subsystem presents a 0. the state of the pin can always be read from the port register by the program. to comply with the i 2 c specification, p0.0 and p0.1 are open drain bidirectional i/o pins with the electrical characteristics listed in the tables that follow. while these differ from astandard ttlo characteristics, they are close enough for the pins to still be used as general-purpose i/o in non-i 2 c applications. port 0 also provides alternate functions for programming the eprom memory as follows: 6 7 n/a v pp (p0.2) programming voltage input. (see note 1.) 7 8 i oe/pgm (p0.1) input which specifies verify mode (output enable) or the program mode. oe/pgm = 1 output enabled (verify mode). oe/pgm = 0 program mode. 8 9 i asel (p0.0) input which indicates which bits of the eprom address are applied to port 3. asel = 0 low address byte available on port 3. asel = 1 high address byte available on port 3 (only the three least significant bits are used). 7 8 i/o sda (p0.1) i 2 c data. 8 9 i/o scl (p0.0) i 2 c clock. p1.0p1.7 1320 1520, 23, 24 i/o port 1: port 1 is an 8-bit bidirectional i/o port with internal pull-ups. port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (see dc electrical characteristics: i il ). port 1 serves to output the addressed eprom contents in the verify mode and accepts as inputs the value to program into the selected address during the program mode. port 1 also serves the special function features of the 80c51 family as listed below: 18 20 i int0 (p1.5): external interrupt. 19 23 i int1 (p1.6): external interrupt. 20 24 i t0 (p1.7): timer 0 external input. p3.0p3.7 51, 2321 6, 41, 2725 i/o port 3: port 3 is an 8-bit bidirectional i/o port with internal pull-ups. port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. as inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (see dc electrical characteristics: i il ). port 3 also functions as the address input for the eprom memory location to be programmed (or verified). the 11-bit address is multiplexed into this port as specified by p0.0/asel. rst 9 11 i reset: a high on this pin for two machine cycles while the oscillator is running, resets the device. an internal diffused resistor to v ss permits a power-on reset using only an external capacitor to v cc . after the device is reset, a 10-bit serial sequence, sent lsb first, applied to reset, places the device in the programming state allowing programming address, data and v pp to be applied for programming or verification purposes. the reset serial sequence must be synchronized with the x1 input. x1 11 13 i crystal 1: input to the inverting oscillator amplifier and input to the internal clock generator circuits. x1 also serves as the clock to strobe in a serial bit stream into reset to place the device in the programming state. x2 10 12 o crystal 2: output from the inverting oscillator amplifier. note: 1. when p0.2 is at or close to 0v it may affect the internal rom operation. we recommend that p0.2 be tied to v cc via a small pullup (e.g., 2k w ).
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 6 absolute maximum ratings 1, 2 parameter rating unit storage temperature range 65 to +150 c voltage from v cc to v ss 0.5 to +6.5 v voltage from any pin to v ss (except v pp ) 0.5 to v cc + 0.5 v power dissipation 1.0 w voltage on v pp pin to v ss 0 to +13.0 v maximum i ol per i/o pin 10 ma notes: 1. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any conditions other than those described in the ac and dc electrical characteri stics section of this specification is not implied. 2. this product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. dc electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10% for 87C751, v cc = 5v 10% for 83c751, v ss = 0v 1 symbol parameter test conditions limits unit symbol parameter test conditions min max unit v il input low voltage, except sda, scl 0.5 0.2v dd 0.1 v v ih input high voltage, except x1, rst 0.2v cc +0.9 v cc +0.5 v v ih1 input high voltage, x1, rst 0.7v cc v cc +0.5 v sda, scl, p0.2 v il1 input low voltage 0.5 0.3v cc v v ih2 input high voltage 0.7v cc v cc +0.5 v v ol output low voltage, ports 1 and 3 i ol = 1.6ma 2 0.45 v v ol1 output low voltage, port 0.2 i ol = 3.2ma 2 0.45 v v oh output high voltage, ports 1 and 3 i oh = 60 m a 2.4 v i oh = 25 m a 0.75v cc v i oh = 10 m a 0.9v cc v port 0.0 and 0.1 (i 2 c) drivers v ol2 output low voltage i ol = 3ma 0.4 v driver, receiver combined: (over v cc range) c capacitance 10 pf i il logical 0 input current, ports 1 and 3 v in = 0.45v 50 m a i tl logical 1 to 0 transition current, ports 1 and 3 3 v in = 2v (0 to 70 c) v in = 2v (40 to +85 c) 650 750 m a m a i li input leakage current, port 0 0.45 < v in < v cc 10 m a r rst internal pull-down resistor 25 175 k w c io pin capacitance test freq = 1mhz, t amb = 25 c 10 pf i pd power-down current 4 v cc = 2 to v cc max 50 m a v pp v pp program voltage (for 87C751 only) v ss = 0v v cc = 5v 10% t amb = 21 c to 27 c 12.5 13.0 v i pp program current (for 87C751 only) v pp = 13.0v 50 ma i cc supply current (see figure 2) notes to dc electrical characteristics on next page.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 7 notes to dc electrical characteristics: 1. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 2. under steady state (non-transient) conditions, i ol must be externally limited as follows: maximum i ol per port pin: 10ma (note: this is 85 c spec.) maximum i ol per 8-bit port: 26ma maximum total i ol for all outputs: 67ma if i ol exceeds the test condition, v ol may exceed the related specification. pins are not guaranteed to sink current greater than the listed test conditions. 3. pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. the transition current r eaches its maximum value when v in is approximately 2v. 4. power-down i cc is measured with all output pins disconnected; port 0 = v cc ; x2, x1 n.c.; rst = v ss . 5. active i cc is measured with all output pins disconnected; x1 driven with t clch , t chcl = 5ns, v il = v ss + 0.5v, v ih = v cc 0.5v; x2 n.c.; rst = port 0 = v cc . i cc will be slightly higher if a crystal oscillator is used. 6. idle i cc is measured with all output pins disconnected; x1 driven with t clch , t chcl = 5ns, v il = v ss + 0.5v, v ih = v cc 0.5v; x2 n.c.; port 0 = v cc ; rst = v ss . ac electrical characteristics t amb = 0 c to +70 c or 40 c to +85 c, v cc = 5v 10% for 87C751, v cc = 5v 10% for 83c751, v ss = 0v 1, 2 12mhz clock variable clock symbol parameter min max min max unit 1/t clcl oscillator frequency: 3.5 12 mhz 3.5 16 mhz external clock (figure 1) t chcx high time 20 20 ns t clcx low time 20 20 ns t clch rise time 20 20 ns t chcl fall time 20 20 ns notes: 1. parameters are valid over operating temperature range unless otherwise specified. all voltages are with respect to v ss unless otherwise noted. 2. load capacitance for ports = 80pf.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 8 explanation of the ac symbols each timing symbol has five characters. the first character is always `t' (= time). the other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. the designations are: c clock d input data h logic level high l logic level low q output data t time v valid x no longer a valid logic level z float t chcl t clcl t clch t chcx v cc 0.5 0.45v 0.2 v cc + 0.9 0.2 v cc 0.1 t clcx su00297 figure 1. external clock drive 4mhz 8mhz 12mhz 16mhz freq max active i cc 5 typ active i cc 5 max idle i cc 6 typ idle i cc 6 i cc (ma) 2 4 6 8 10 12 14 16 18 20 22 su00298 figure 2. i cc vs. freq maximum i cc values taken at v cc max and worst case temperature. typical i cc values taken at v cc = 5.0v and 25 c. notes 5 and 6 refer to dc electrical characteristics.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 9 oscillator characteristics x1 and x2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator. to drive the device from an external clock source, x1 should be driven while x2 is left unconnected. there are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. however, minimum and maximum high and low times specified in the data sheet must be observed. reset a reset is accomplished by holding the rst pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. to insure a good power-up reset, the rst pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. at power-up, the voltage on v cc and rst must come up at the same time for a proper start-up. idle mode in idle mode, the cpu puts itself to sleep while all of the on-chip peripherals stay active. the instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. the cpu contents, the on-chip ram, and all of the special function registers remain intact during this mode. the idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. power-down mode in the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. only the contents of the on-chip ram are preserved. a hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register pcon. table 1. external pin status during idle and power-down modes mode port 0 port 1 port 2 idle data data data power-down data data data differences between the 8xc751 and the 80c51 memory organization the central processing unit (cpu) manipulates operands in two address spaces as shown in figure 3. the part's internal memory space consists of 2k bytes of program memory, and 64 bytes of data ram overlapped with the 128-byte special function register area. the differences from the 80c51 are in ram size (64 bytes vs. 128 bytes), in external ram access (not available on the 83c751), in internal rom size (2k bytes vs. 4k bytes), and in external program memory expansion (not available on the 83c751). the 128-byte special function register (sfr) space is accessed as on the 80c51 with some of the registers having been changed to reflect changes in the 83c751 peripheral functions. the stack may be located anywhere in internal ram by loading the 8-bit stack pointer (sp). it should be noted that stack depth is limited to 64 bytes, the amount of available ram. a reset loads the stack pointer with 07 (which is pre-incremented on a push instruction). special function registers internal data ram (ffh) 255 (80h) 128 (3fh) 63 (00h) 0 su00299 figure 3. memory map program memory on the 8xc751, program memory is 2048 bytes long and is not externally expandable, so the 80c51 instructions movx, ljmp, and lcall are not implemented. the only fixed locations in program memory are the addresses at which execution is taken up in response to reset and interrupts, which are as follows: program memory event address reset 000 external int0 003 counter/timer 0 00b external int1 013 timer i 01b i 2 c serial 023 counter/timer subsystem the 8xc751 has one counter/timer called timer/counter 0. its operation is similar to mode 2 operation on the 80c51, but is extended to 16 bits with 16 bits of autoload. the controls for this counter are centralized in a single register called tcon. a watchdog timer, called timer i, is for use with the i 2 c subsystem. in i 2 c applications, this timer is dedicated to time-generation and bus monitoring of the i 2 c. in non-i 2 c applications, it is available for use as a fixed time-base. counter timer special function register the counter/timer has only one mode of operation, so the tmod sfr is not used. there is also only one counter/timer, so there is no need for the tl1 and th1 sfrs found on the 80c51. these have been replaced on the 83c751 by rtl and rth, the counter/timer reload registers. table 3 shows the special function registers, their locations, and reset values. interrupt subsystem fixed priority the ip register and the 2-level interrupt system of the 80c51 are eliminated. simultaneous interrupt conditions are resolved by a single-level, fixed priority as follows: highest priority: pin int0 counter/timer flag 0 pin int1 timer i lowest priority: serial i 2 c
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 10 special function register interrupt subsystem because the interrupt structure is single level on the 83c751, there is no need for the ip sfr, so it is not used. serial communications the 8xc751 contains an i 2 c serial communications port instead of the 80c51 uart. the i 2 c serial port is a single bit hardware interface with all of the hardware necessary to support multimaster and slave operations. also included are receiver digital filters and timer (timer i) for communication watch-dog purposes. the i 2 c serial port is controlled through four special function registers; i 2 c control, i 2 c data, i 2 c status, and i 2 c configuration. special function register serial communications the 83c751 contains many of the special function registers (sfr) that are found on the 80c51. due to the different peripheral features on the 83c751, there are several additional sfrs and several that have been changed. since the standard uart found on the 80c51 has been replaced by the i 2 c serial interface, the uart sfrs, scon, and sbuf have been replaced by i2con and i2dat, and two additional i 2 c registers have been added (i2sta and i2cfg). i/o port latches (p0, p1, p3) the port latches function the same as those on the 80c51. since there is no port 2 on the 83c751, the p2 latch is not used. port 0 on the 83c751 has only 3 bits, so only 3 bits of the p0 sfr have a useful function. special function register i/o port latches there is no port2 on the 8xc751, so p2 is not used. also, only 3 bits of p0 sfr have a useful function. data pointer (dptr) the data pointer (dptr) consists of a high byte (dph) and a low byte (dpl). in the 80c51 this register allows the access of external data memory using the movx instruction. since the 83c751 does not support movx or external memory accesses, this register is generally used as a 16-bit offset pointer of the accumulator in a movc instruction. dptr may also be manipulated as two independent 8-bit registers. table 2. i 2 c special function register addresses register address bit address name symbol address msb lsb i 2 c control i2con 98 9f 9e 9d 9c 9b 9a 99 98 i 2 c data i2dat 99 i 2 c configuration i2cfg d8 df de dd dc db da d9 d8 i 2 c status i2sta f8 ff fe fd fc fb fa f9 f8 rom code submission when submitting rom code for the 80c751, the following must be specified: 1. 2k byte user rom data address content bit(s) comment 0000h to 07ffh data 7:0 user rom data
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 11 table 3. 8xc751 special function registers symbol description direct address bit address, symbol, or alternative port function msb lsb reset value acc* accumulator e0h e7 e6 e5 e4 e3 e2 e1 e0 00h b* b register f0h f7 f6 f5 f4 f3 f2 f1 f0 00h dptr: dph dpl data pointer (2 bytes) high byte low byte 83h 82h 00h 00h df de dd dc db da d9 d8 i 2 cfg*# i 2 c configuration d8h/rd slaven mastrq 0 tirun ct1 ct0 0000xx00b wr slaven mastrq clrti tirun ct1 ct0 9f 9e 9d 9c 9b 9a 99 98 i 2 con*# i 2 c control 98h/rd rdat atn drdy arl str stp master 81h wr cxa idle cdr carl cstr cstp xstr xstp i 2 dat# i 2 c data 99h/rd rdat 0 0 0 0 0 0 0 80h wr xdat x x x x x x x ff fe fd fc fb fa f9 f8 i 2 sta*# i 2 c status f8h idle xdata xactv makstr makstp xstr xstp x0100000b af ae ad ac ab aa a9 a8 ie*# interrupt enable abh ea ei2 et1 ex1 et0 ex0 00h 82 81 80 p0*# port 0 80h sda scl xxxxx111b 97 96 95 94 93 92 91 90 p1* port 1 90h t0 int1 int0 ffh p3* port 3 b0h b7 b6 b5 b4 b3 b2 b1 b0 ffh pcon# power control 87h pd idl xxxxxx00b d7 d6 d5 d4 d3 d2 d1 d0 psw* program status word d0h cy ac f0 rs1 rs0 ov p 00h sp stack pointer 81h 07h 8f 8e 8d 8c 8b 8a 89 88 tcon*# timer/counter control 88h gate c/t tf tr ie0 it0 ie1 it1 00h tl# timer low byte 8ah 00h th# timer high byte 8ch 00h rtl# timer low reload 8bh 00h rth# timer high reload 8dh 00h * sfrs are bit addressable. # sfrs are modified from or added to the 80c51 sfrs.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 12 i/o port structure the 8xc751 has two 8-bit ports (ports 1 and 3) and one 3-bit port (port 0). all three ports on the 8xc751 are bidirectional. each consists of a latch (special function register p0, p1, p3), an output driver, and an input buffer. three port 1 pins and two port 0 pins are multifunctional. in addition to being port pins, these pins serve the function of special features as follows: port pinalternate function p0.0 i 2 c clock (scl) p0.1 i 2 c data (sda) p1.5 int0 (external interrupt 0 input) p1.6 int1 (external interrupt 1 input) p1.7 t0 (timer 0 external input) ports 1 and 3 are identical in structure to the same ports on the 80c51. the structure of port 0 on the 8xc751 is similar to that of the 80c51 but does not include address/data input and output circuitry. as on the 80c51, ports 1 and 3 are quasi-bidirectional while port 0 is bidirectional with no internal pullups. timer/counter the 8xc751 has two timers: a 16-bit timer/counter and a 10-bit fixed-rate timer. the 16-bit timer/counter's operation is similar to mode 2 operation on the 80c51, but is extended to 16 bits. the timer/counter is clocked by either 1/12 the oscillator frequency or by transitions on the t0 pin. the c/t pin in special function register tcon selects between these two modes. when the tcon tr bit is set, the timer/counter is enabled. register pair th and tl are incremented by the clock source. when the register pair overflows, the register pair is reloaded with the values in registers rth and rtl. the value in the reload registers is left unchanged. see the 83c751 counter/timer block diagram in figure 4. the tf bit in special function register tcon is set on counter overflow and, if the interrupt is enabled, will generate an interrupt. tcon register msb lsb gate c/t tf tr ie0 it0 ie1 it1 gate 1 timer/counter is enabled only when int0 pin is high, and tr is 1. 0 timer/counter is enabled when tr is 1. c/t 1 counter/timer operation from t0 pin. 0 timer operation from internal clock. tf 1 set on overflow of th. 0 cleared when processor vectors to interrupt routine and by reset. tr 1 timer/counter enabled. 0 timer/counter disabled. ie0 1 edge detected in int0 . it0 1 int0 is edge triggered. 0 int0 is level sensitive. ie1 1 edge detected on int1 . it1 1 int1 is edge triggered. 0 int1 is level sensitive. these flags are functionally identical to the corresponding 80c51 flags, except that there is only one timer on the 83c751 and the flags are therefore combined into one register. note that the positions of the ie0/it0 and ie1/it1 bits are transposed from the positions used in the standard 80c51 tcon register. timer i is used to control the timing of the i 2 c bus and also to detect a abus lockedo condition, by causing an interrupt when nothing happens on the i 2 c bus for an inordinately long period of time while a transmission is in progress. if the interrupt does not occur, the program can attempt to correct the fault and allow the last i 2 c transmission to be repeated. the i 2 c watchdog timer, timer i, is also available as a general-purpose fixed-rate timer when the i 2 c interface is not being used. a clock rate of 1/12 the oscillator frequency forms the input to the timer. timer i has a timeout interval of 1024 machine cycles when used as a fixed-rate timer. osc 12 tl th tf rtl rth t0 pin tr gate int0 pin int. c/t = 0 c/t = 1 reload su00300 figure 4. 83c751 counter/timer block diagram
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 13 i 2 c serial interface the i 2 c bus uses two wires (sda and scl) to transfer information between devices connected to the bus. the main features of the bus are: ? bidirectional data transfer between masters and slaves ? serial addressing of slaves (no added wiring) ? acknowledgment after each transferred byte ? multimaster bus ? arbitration between simultaneously transmitting masters without corruption of serial data on bus ? the 82b715 extends communication distance to 100 feet (30m). a large family of i 2 c compatible ics is available. see the i 2 c section of this manual for more details on the bus and available ics. the 83c751 i 2 c subsystem includes hardware to simplify the software required to drive the i 2 c bus. the hardware is a single bit interface which in addition to including the necessary arbitration and framing error checks, includes clock stretching and a bus timeout timer. the interface is synchronized to software either through polled loops or interrupts. refer to the application note an422, in section 4, entitled ausing the 8xc751 microcontroller as an i 2 c bus mastero for additional discussion of the 83c751 i 2 c interface and sample driver routines. six time spans are important in i 2 c operation and are insured by timer i: ? the minimum high time for scl when this device is the master. ? the minimum low time for scl when this device is a master. this is not very important for a single-bit hardware interface like this one, because the scl low time is stretched until the software responds to the i 2 c flags. the software response time normally meets or exceeds the min lo time. in cases where the software responds within min hi + min lo) time, timer i will ensure that the minimum time is met. ? the minimum scl high to sda high time in a stop condition. ? the minimum sda high to sda low time between i 2 c stop and start conditions (4.7 m s, see spec.). ? the minimum sda low to scl low time in a start condition. ? the maximum scl change time while an i 2 c frame is in progress. a frame is in progress between a start condition and the following stop condition. this time span serves to detect a lack of software response on this 8xc751 as well as external i 2 c problems. scl astuck lowo indicates a faulty master or slave. scl astuck higho may mean a faulty device, or that noise induced onto the i 2 c bus caused all masters to withdraw from i 2 c arbitration. the first five of these times are 4.7 m s (see i 2 c specification) and are covered by the low order three bits of timer i. timer i is clocked by the 8xc751 oscillator, which can vary in frequency from 0.5 to 16mhz. timer i can be preloaded with one of four values to optimize timing for different oscillator frequencies. at lower frequencies, software response time is increased and will degrade maximum performance of the i 2 c bus. see special function register i2cfg description for prescale values (ct0, ct1). the maximum scl change time is important, but its exact span is not critical. the complete 10 bits of timer i are used to count out the maximum time. when i 2 c operation is enabled, this counter is cleared by transitions on the scl pin. the timer does not run between i 2 c frames (i.e., whenever reset or stop occurred more recently than the last start). when this counter is running, it will carry out after 1020 to 1023 machine cycles have elapsed since a change on scl. a carry out causes a hardware reset of the 83c751 i 2 c interface and generates an interrupt if the timer i interrupt is enabled. in cases where the bus hangup is due to a lack of software response by this 83c751, the reset releases scl and allows i 2 c operation among other devices to continue. i 2 c interrupts if i 2 c interrupts are enabled (ea and ei2 are both set to 1), an i 2 c interrupt will occur whenever the atn flag is set by a start, stop, arbitration loss, or data ready condition (refer to the description of atn following). in practice, it is not efficient to operate the i 2 c interface in this fashion because the i 2 c interrupt service routine would somehow have to distinguish between hundreds of possible conditions. also, since i 2 c can operate at a fairly high rate, the software may execute faster if the code simply waits for the i 2 c interface. typically, the i 2 c interrupt should only be used to indicate a start condition at an idle slave device, or a stop condition at an idle master device (if it is waiting to use the i 2 c bus). this is accomplished by enabling the i 2 c interrupt only during the aforementioned conditions. i 2 c register i2con 765432 1 0 read rdat atn drdy arl str stp master write cxa idle cdr carl cstr cstp xstr xstp reading i2con rdat the data from sda is captured into areceive datao whenever a rising edge occurs on scl. rdat is also available (with seven low-order zeros) in the i2dat register. the difference between reading it here and there is that reading i2dat clears drdy, allowing the i 2 c to proceed on to another bit. typically, the first seven bits of a received byte are read from i2dat, while the 8th is read here. then i2dat can be written to send the ack bit and clear drdy. atn aattentiono is 1 when one or more of drdy, arl, str, or stp is 1. thus, atn comprises a single bit that can be tested to release the i 2 c service routine from a await loop.o drdy adata readyo (and thus atn) is set when a rising edge occurs on scl, except at idle slave. drdy is cleared by writing cdr = 1, or by writing or reading the i2dat register. the following low period on scl is stretched until the program responds by clearing drdy.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 14 checking atn and drdy when a program detects atn = 1, it should next check drdy. if drdy = 1, then if it receives the last bit, it should capture the data from rdat (in i2dat or i2con). next, if the next bit is to be sent, it should be written to i2dat. one way or another, it should clear drdy and then return to monitoring atn. note that if any of arl, str, or stp is set, clearing drdy will not release scl to high, so that the i 2 c will not go on to the next bit. if a program detects atn = 1, and drdy = 0, it should go on to examine arl, str, and stp. arl aarbitration losso is 1 when transmit active was set, but this 83c751 lost arbitration to another transmitter. transmit active is cleared when arl is 1. there are four separate cases in which arl is set. 1. if the program sent a 1 or repeated start, but another device sent a 0, or a stop, so that sda is 0 at the rising edge of scl. (if the other device sent a stop, the setting of arl will be followed shortly by stp being set.) 2. if the program sent a 1, but another device sent a repeated start, and it drove sda low before the 83c751 could drive scl low. (this type of arl is always accompanied by str = 1.) 3. in master mode, if the program sent a repeated start, but another device sent a 1, and it drove scl low before this 83c751 could drive sda low. 4. in master mode, if the program sent stop, but it could not be sent because another device sent a 0. str astarto is set to a 1 when an i 2 c start condition is detected at a non-idle slave or at a master. (str is not set when an idle slave becomes active due to a start bit; the slave has nothing useful to do until the rising edge of scl sets drdy.) stp astopo is set to 1 when an i 2 c stop condition is detected at a non-idle slave or at a master. (stp is not set for a stop condition at an idle slave.) master amastero is 1 if this 83c751 is currently a master on the i 2 c. master is set when mastrq is 1 and the bus is not busy (i.e., if a start bit hasn't been received since reset or a atimer io time-out, or if a stop has been received since the last start). master is cleared when arl is set, or after the software writes mastrq = 0 and then xstp = 1. writing i2con typically, for each bit in an i 2 c message, a service routine waits for atn = 1. based on drdy, arl, str, and stp, and on the current bit position in the message, it may then write i2con with one or more of the following bits, or it may read or write the i2dat register. cxa writing a 1 to aclear xmit activeo clears the transmit active state. (reading the i2dat register also does this.) regarding transmit active transmit active is set by writing the i2dat register, or by writing i2con with xstr = 1 or xstp = 1. the i 2 c interface will only drive the sda line low when transmit active is set, and the arl bit will only be set to 1 when transmit active is set. transmit active is cleared by reading the i2dat register, or by writing i2con with cxa = 1. transmit active is automatically cleared when arl is 1. idle writing 1 to aidleo causes a slave's i 2 c hardware to ignore the i 2 c until the next start condition (but if mastrq is 1, then a stop condition will make the 83c751 into a master). cdr writing a 1 to aclear data readyo clears drdy. (reading or writing the i2dat register also does this.) carl writing a 1 to aclear arbitration losso clears the arl bit. cstr writing a 1 to aclear starto clears the str bit. cstp writing a 1 to aclear stopo clears the stp bit. note that if one or more of drdy, arl, str, or stp is 1, the low time of scl is stretched until the service routine responds by clearing them. xstr writing 1s to axmit repeated starto and cdr tells the i 2 c hardware to send a repeated start condition. this should only be at a master. note that xstr need not and should not be used to send an ainitialo (nonrepeated) start; it is sent automatically by the i 2 c hardware. writing xstr = 1 includes the effect of writing i2dat with xdat = 1; it sets transmit active and releases sda to high during the scl low time. after scl goes high, the i 2 c hardware waits for the suitable minimum time and then drives sda low to make the start condition. xstp writing 1s to axmit stopo and cdr tells the i 2 c hardware to send a stop condition. this should only be done at a master. if there are no more messages to initiate, the service routine should clear the mastrq bit in i2cfg to 0 before writing xstp with 1. writing xstp = 1 includes the effect of writing i2dat with xdat = 0; it sets transmit active and drives sda low during the scl low time. after scl goes high, the i 2 c hardware waits for the suitable minimum time and then releases sda to high to make the stop condition. note: because of the manner in which register bit addressing is implemented in the 80c51 family, the i2con register should never be altered by use of the setb, clr, cpl, mov (bit), or jbc instructions. this is due to the fact that read and write functions of this register are different. testing of i2con bits via the jb and jnb instructions is supported.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 15 i 2 c register i2dat 76543210 read rdat 0 0 0 0 0 0 0 write xdat x x x x x x x rdat areceive datao is captured from sda every rising edge of scl. reading i2dat also clears drdy and the transmit active state. xdat axmit datao sets the data for the next bit. writing i2dat also clears drdy and sets the transmit active state. regarding software response time because the 83c751 can run at 16mhz, and because the i 2 c interface is optimized for high-speed operation, it is quite likely that an i 2 c service routine will sometimes respond to drdy (which is set at a rising edge of scl) and write i2dat before scl has gone low again. if xdat were applied directly to sda, this situation would produce an i 2 c protocol violation. the programmer need not worry about this possibility because xdat is applied to sda only when scl is low. conversely, a program that includes an i 2 c service routine may take a long time to respond to drdy. typically, an i 2 c routine operates on a flag-polling basis during a message, with interrupts from other peripheral functions enabled. if an interrupt occurs, it will delay the response of the i 2 c service routine. the programmer need not worry about this very much either, because the i 2 c hardware stretches the scl low time until the service routine responds. the only constraint on the response is that it must not exceed the timer i time-out, which is at least 765 microseconds. i 2 c register i2cfg 7 6 5 4 3210 read slaven mastrq 0 tirun ct1 ct0 write slaven mastrq clrti tirun ct1 ct0 slaven writing a 1 to aslave enableo enables the slave functions of the i 2 c subsystem. if slaven and mastrq are 0, the i 2 c hardware is disabled. this bit is cleared to 0 by reset and by an i 2 c time-out. mastrq writing a 1 to amastrqo requests mastership of the i 2 c. if a frame from another master is in progress when this bit is changed from 0 to 1, action is delayed until a stop condition is detected. then, or immediately if a frame is not in progress, a start condition is sent and drdy is set (thus making atn 1 and generating an i 2 c interrupt). when a master wishes to release mastership status of the i 2 c, it writes a 1 to xstp in i2con. mastrq is cleared by reset and by an i 2 c time-out. clrti writing a 1 to this bit clears the timer i interrupt flag. this bit position always reads as a 0. tirun writing a 1 to this bit lets timer i run; a zero stops and clears it. together with slaven, mastrq, and master, this bit determines operational modes as shown in table 4. ct1,0 these two bits are programmed as a function of the osc rate, to optimize the min hi and lo time of scl when this 83c751 is a master on the i 2 c. the time value determined by these bits controls both of these parameters, and also the timing for stop and start conditions. these bits are cleared to 00 by reset. values to be used in the ct1 and ct0 bits are shown in table 5. to allow the i 2 c bus to run at the maximum rate for a particular oscillator frequency, compare the actual oscillator rate to the f osc max column in the table. the value for ct1 and ct0 is found in the first line of the table where f osc max is greater than or equal to the actual frequency. the table also shows the osc/12 count for various settings of ct1/ct0. this allows calculation of the actual minimum high and low times for scl as follows: scl min high/low time (in microseconds) = 12 * count / osc (in mhz) for instance, at a 16mhz frequency, with ct1/ct0 set to 10, the minimum scl high and low times will be 5.25 m s. the table also shows the timer i timeout period (given in machine cycles) for each ct1/ct0 combination. the timeout period varies because of the way in which minimum scl high and low times are measured. when the i 2 c interface is operating, timer i is preloaded at every scl transition with a value dependent upon ct1/ct0. the preload value is chosen such that a minimum scl high or low time has elapsed when timer i reaches a count of 008 (the actual value preloaded into timer i is 8 minus the osc/12 count).
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 16 table 4. interaction of tirun with slaven, mastrq, and master slaven, mastrq, master tirun operating mode all 0 0 the i 2 c interface is disabled. timer i is cleared and does not run. this is the state assumed after a reset. if an i 2 c application wants to ignore the i 2 c at certain times, it should write slaven, mastrq, and tirun all to zero. all 0 1 the i 2 c interface is disabled. timer i operates as a free-running time base. use this mode only in non-i 2 c applications. any or all 1 0 the i 2 c interface is enabled. the 3 low-order bits of timer i run for min-time generation, but the hi-order bits do not, so that there is no checking for i 2 c being ahung.o this configuration can be used for very slow i 2 c operation. any or all 1 1 the i 2 c interface is enabled. timer i runs during frames on the i 2 c, and is cleared by transitions on scl, and by start and stop conditions. this is the normal state for i 2 c operation. table 5. ct1, ct0 values ct1, ct0 osc/12 count f osc max timeout period 10 7 16.8mhz 1023 cycles 01 6 14.4mhz 1022 cycles 00 5 12.0mhz 1021 cycles 11 4 9.6mhz 1020 cycles i 2 c register i2sta read only 7654 3 2 10 idle xdata xactv makstr makstp xstr xstp msb lsb this register is read only and reflects the internal status of the i 2 c hardware. idle, xstr, and xstp reflect the status of the like named bits in the i2con register. xdata the content of the transmitter buffer. xactv transmitter active. makstr this bit is high while the hardware is effecting a start condition. makstp this bit is high while the hardware is effecting a stop condition. xstr this bit is active while the hardware is effecting a repeated start condition. xstp this bit is active while the hardware is effecting a repeated stop condition. interrupts the interrupt structure is a five-source, one-level interrupt system. interrupt sources common to the 80c51 are the external interrupts (int0 , int1 ) and the timer/counter interrupt (et0). the i 2 c interrupt (ei2) and timer i interrupt (eti) are the other two interrupt sources. the interrupt sources are listed below in their order of polling sequence priority. upon interrupt or reset the program counter is loaded with specific values for the appropriate interrupt service routine in program memory. these values are: program memory event address priority reset 000 highest int0 003 counter/timer 0 00b int1 013 timer i 01b i 2 c 023 lowest the interrupt enable register (ie) is used to individually enable or disable the five sources. bit ea in the interrupt enable register can be used to globally enable or disable all interrupt sources. the interrupt enable register is described below. all other interrupt details are based on the 80c51 interrupt architecture. interrupt enable register 76543210 ea x x ei2 eti ex1 et0 ex0 symbol position function ea ie.7 disables all interrupts. if ea = 0, no interrupt will be acknowledged. if ea = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit ie.6 reserved ie.5 reserved ei2 ie.4 enables or disables the i 2 c interrupt. if ei2 = 0, the i 2 c interrupt is disabled eti ie.3 enables or disables the timer i overflow interrupt. if eti = 0, the timer i interrupt is disabled. ex1 ie.2 enables or disables external interrupt 1. if ex1 = 0, external interrupt 1 is disabled. et0 ie.1 enables or disables the timer 0 overflow interrupt. if et0 = 0, thetimer 0 interrupt is disabled. ex0 ie.0 enables or disables external interrupt 0. if ex0 = 0, external interrupt 0 is disabled.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 17 87C751 programming considerations eprom characteristics the 87C751 is programmed by using a modified quick-pulse programming algorithm similar to that used for devices such as the 87c451 and 87c51. it differs from these devices in that a serial data stream is used to place the 87C751 in the programming mode. figure 5 shows a block diagram of the programming configuration for the 87C751. port pin p0.2 is used as the programming voltage supply input (v pp signal). port pin p0.1 is used as the program (pgm/) signal. this pin is used for the 25 programming pulses. port 3 is used as the address input for the byte to be programmed and accepts both the high and low components of the eleven bit address. multiplexing of these address components is performed using the asel input. the user should drive the asel input high and then drive port 3 with the high order bits of the address. asel should remain high for at least 13 clock cycles. asel may then be driven low which latches the high order bits of the address internally. the high address should remain on port 3 for at least two clock cycles after asel is driven low. port 3 may then be driven with the low byte of the address. the low address will be internally stable 13 clock cycles later. the address will remain stable provided that the low byte placed on port 3 is held stable and asel is kept low. note: asel needs to be pulsed high only to change the high byte of the address. port 1 is used as a bidirectional data bus during programming and verify operations. during programming mode, it accepts the byte to be programmed. during verify mode, it provides the contents of the eprom location specified by the address which has been supplied to port 3. the xtal1 pin is the oscillator input and receives the master system clock. this clock should be between 1.2 and 6mhz. the reset pin is used to accept the serial data stream that places the 87C751 into various programming modes. this pattern consists of a 10-bit code with the lsb sent first. each bit is synchronized to the clock input, x1. programming operation figures 6 and 7 show the timing diagrams for the program/verify cycle. reset should initially be held high for at least two machine cycles. p0.1 (pgm/) and p0.2 (v pp ) will be at v oh as a result of the reset operation. at this point, these pins function as normal quasi-bidirectional i/o ports and the programming equipment may pull these lines low. however, prior to sending the 10-bit code on the reset pin, the programming equipment should drive these pins high (v ih ). the reset pin may now be used as the serial data input for the data stream which places the 87C751 in the programming mode. data bits are sampled during the clock high time and thus should only change during the time that the clock is low. following transmission of the last data bit, the reset pin should be held low. next the address information for the location to be programmed is placed on port 3 and asel is used to perform the address multiplexing, as previously described. at this time, port 1 functions as an output. a high voltage v pp level is then applied to the v pp input (p0.2). (this sets port 1 as an input port). the data to be programmed into the eprom array is then placed on port 1. this is followed by a series of programming pulses applied to the pgm/ pin (p0.1). these pulses are created by driving p0.1 low and then high. this pulse is repeated until a total of 25 programming pulses have occurred. at the conclusion of the last pulse, the pgm/ signal should remain high. the v pp signal may now be driven to the v oh level, placing the 87C751 in the verify mode. (port 1 is now used as an output port). after four machine cycles (48 clock periods), the contents of the addressed location in the eprom array will appear on port 1. the next programming cycle may now be initiated by placing the address information at the inputs of the multiplexed buffers, driving the v pp pin to the v pp voltage level, providing the byte to be programmed to port1 and issuing the 26 programming pulses on the pgm/ pin, bringing v pp back down to the v c level and verifying the byte. programming modes the 87C751 has four programming features incorporated within its eprom array. these include the user eprom for storage of the application's code, a 16-byte encryption key array and two security bits. programming and verification of these four elements are selected by a combination of the serial data stream applied to the reset pin and the voltage levels applied to port pins p0.1 and p0.2. the various combinations are shown in table 6. encryption key table the 87C751 includes a 16-byte eprom array that is programmable by the end user. the contents of this array can then be used to encrypt the program memory contents during a program memory verify operation. when a program memory verify operation is performed, the contents of the program memory location is xnor'ed with one of the bytes in the 16-byte encryption table. the resulting data pattern is then provided to port 1 as the verify data. the encryption mechanism can be disable, in essence, by leaving the bytes in the encryption table in their erased state (ffh) since the xnor product of a bit with a logical one will result in the original bit. the encryption bytes are mapped with the code memory in 16-byte groups. the first byte in code memory will be encrypted with the first byte in the encryption table; the second byte in code memory will be encrypted with the second byte in the encryption table and so forth up to and including the 16the byte. the encryption repeats in 16-byte groups; the 17th byte in the code memory will be encrypted with the first byte in the encryption table, and so forth. security bits two security bits, security bit 1 and security bit 2, are provided to limit access to the user eprom and encryption key arrays. security bit 1 is the program inhibit bit, and once programmed performs the following functions: 1. additional programming of the user eprom is inhibited. 2. additional programming of the encryption key is inhibited. 3. verification of the encryption key is inhibited. 4. verification of the user eprom and the security bit levels may still be performed. (if the encryption key array is being used, this security bit should be programmed by the user to prevent unauthorized parties from reprogramming the encryption key to all logical zero bits. such programming would provide data during a verify cycle that is the logical complement of the user eprom contents). security bit 2, the verify inhibit bit, prevents verification of both the user eprom array and the encryption key arrays. the security bit levels may still be verified.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 18 programming and verifying security bits security bits are programmed employing the same techniques used to program the user eprom and key arrays using serial data streams and logic levels on port pins indicated in table 6. when programming either security bit, it is not necessary to provide address or data information to the 87C751 on ports 1 and 3. verification occurs in a similar manner using the reset serial stream shown in table 6. port 3 is not required to be driven and the results of the verify operation will appear on ports 1.6 and 1.7. ports 1.7 contains the security bit 1 data and is a logical one if programmed and a logical zero if not programmed. likewise, p1.6 contains the security bit 2 data and is a logical one if programmed and a logical zero if not programmed. erasure characteristics erasure of the eprom begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. for this and secondary effects, it is recommended that an opaque label be placed over the window. for elevated temperature or environments where solvents are being used, apply kapton tape flourless part number 23455 or equivalent. the recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15w-s/cm 2 . exposing the eprom to an ultraviolet lamp of 12,000 m w/cm 2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. erasure leaves the array in an all 1s state. table 6. implementing program/verify modes operation serial code p0.1 (pgm/) p0.2 (v pp ) program user eprom 296h * v pp verify user eprom 296h v ih v ih program key eprom 292h * v pp verify key eprom 292h v ih v ih program security bit 1 29ah * v pp program security bit 2 298h * v pp verify security bits 29ah v ih v ih note: * pulsed from v ih to v il and returned to v ih . a0a10 address strobe programming pulses v pp /v ih voltage source clk source reset control logic 87C751 p3.0p3.7 p0.0/asel p0.1 p0.2 xtal1 reset v cc v ss p1.0p1.7 +5v data bus su00317 figure 5. programming configuration min 2 machine cycles ten bit serial code bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 undefined undefined xtal1 reset p0.2 p0.1 su00302 figure 6. entry into program/verify modes
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 19 eprom programming and verification t amb = 21 c to +27 c, v cc = 5v 10%, v ss = 0v symbol parameter min max unit 1/t clcl oscillator/clock frequency 1.2 6 mhz t avgl 1 address setup to p0.1 (prog) low 10 m s + 24t clcl t ghax address hold after p0.1 (prog) high 48t clcl t dvgl data setup to p0.1 (prog) low 38t clcl t ghdx data hold after p0.1 (prog) high 36t clcl t shgl v pp setup to p0.1 (prog) low 10 m s t ghsl v pp hold after p0.1 (prog) 10 m s t glgh p0.1 (prog) width 90 110 m s t avqv 2 v pp low (v cc ) to data valid 48t clcl t ghgl p0.1 (prog) high to p0.1 (prog) low 10 m s t masel asel high time 13t clcl t hahld address hold time 2t clcl t haset address setup to asel 13t clcl t adsta low address to valid data 48t clcl notes: 1. address should be valid at least 24t clcl before the rising edge of p0.2 (v pp ). 2. for a pure verify mode, i.e., no program mode in between, t avqv is 14t clcl maximum. 5v 12.75v 5v 25 pulses t shgl t ghsl t glgh t ghgl 98 m s min 10 m s min t masel t haset t adsta t dvgl t ghdx t avqv verify mode program mode verify mode p0.2 (v pp ) p0.1 (pgm ) p0.0 (asel) port 3 port 1 invalid data valid data data to be programmed invalid data valid data high address low address t hahld t avgl su00303 figure 7. program/verify cycle purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011.
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 20 dip24: plastic dual in-line package; 24 leads (300 mil) sot222-1
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 21 plcc28: plastic leaded chip carrer; 28 leads; pedestal sot261-3
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 22 ssop24: plastic shrink small outline package; 24 leads; body width 5.3 mm sot340-1
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 23 notes
philips semiconductors product specification 83c751/87C751 80c51 8-bit microcontroller family 2k/64 otp/rom, i 2 c, low pin count 1998 may 01 24 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. date of release: 05-98 document order number: 9397 750 03845
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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